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Features
* Single Voltage Read/Write Operation: 2.65V to 3.3V (BV), 3.0V to 3.6V (LV) * Access Time - 70 ns * Sector Erase Architecture * * * * * * * * * * * *
- Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout - Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout Fast Word Program Time - 20 s Fast Sector Erase Time - 300 ms Dual-plane Organization, Permitting Concurrent Read while Program/Erase Memory Plane A: Eight 4K Word and Seven 32K Word Sectors Memory Plane B: Twenty-four 32K Word Sectors Erase Suspend Capability - Supports Reading/Programming Data from Any Sector by Suspending Erase of Any Different Sector Low-power Operation - 30 mA Active - 10 A Standby Data Polling, Toggle Bit, Ready/Busy for End of Program Detection VPP Pin for Accelerated Program/Erase Operations RESET Input for Device Initialization Sector Lockdown Support TSOP and CBGA Package Options Top or Bottom Boot Block Configuration Available 128-bit Protection Register
16-megabit (1M x 16/2M x 8) 3-volt Only Flash Memory AT49BV1604A AT49BV1604AT AT49BV1614A AT49LV1614A AT49BV1614AT AT49LV1614AT
Description
The AT49BV/LV16X4A(T) is a 2.65- to 3.3-volt 16-megabit Flash memory organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 39 sectors for erase operations. The device is offered in 48-lead TSOP and 48-ball CBGA packages. The device has CE and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single 2.65V power supply, making it ideally suited for in-system programming.
Pin Configurations
Pin Name A0 - A19 CE OE WE RESET RDY/BUSY VPP I/O0 - I/O14 I/O15 (A-1) BYTE NC VCCQ Function Addresses Chip Enable Output Enable Write Enable Reset READY/BUSY Output Power Supply for Accelerated Program/Erase Operations Data Inputs/Outputs I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode) Selects Byte or Word Mode No Connect Output Power Supply
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1
TSOP Top View CBGA Top View (Ball Down)
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET VPP NC A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 VCCQ GND I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0
1 A
A13
2
3
4
5
6
7
8
A11 A10 A12 I/O14
A8 WE A9 I/O5 I/O6 I/O13
VPP RST A18
A19 A17 A6
A7 A5 A3 CE I/O0 I/O1
A4 A2 A1 A0 GND OE
AT49BV1604A(T)
B
A14
C
A15
D
A16 I/O11 I/O12 I/O4 I/O2 I/O3 VCC I/O8 I/O9 I/O10
E
VCCQ I/O15
F
GND I/O7
TSOP Top View Type 1
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE RESET VPP* NC* RDY/BUSY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE GND I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0
CBGA Top View
1 A
A3 A7 RDY/BUSY WE A17 A6 A5 I/O0 I/O8 I/O9 I/O1 NC* A18 NC I/O2 I/O10 I/O11 I/O3 RESET VPP* A19 I/O5 I/O12 VCC I/O4 A9 A8 A10 A11 I/O7 I/O14 A13 A12 A14 A15 A16 BYTE
2
3
4
5
6
B
A4
C
A2
AT49BV/LV1614A(T)
D
A1
E
A0
F
CE
G
OE I/O13 I/O15/A-1 I/O6 VSS
H
VSS
Note:
*For the AT49BV/LV1614A(T), either pin 13 or pin 14 (TSOP package) or ball B3 or ball C4 (CBGA package) can be connected to VPP or both pins can be unconnected. Accelerated program/erase operations are only achieved if a voltage of 5V 0.5 V or 12V 0.5V is applied to pin 13 (TSOP package) or ball C4 (CBGA package).
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AT49BV1604A(T)/1614A(T)
The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see Sector Lockdown section). The device is segmented into two memory planes. Reads from memory plane B may be performed even while program or erase functions are being executed in memory plane A and vice versa. This operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend feature. This feature will put the erase on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the same memory plane. There is no reason to suspend the erase operation if the data to be read is in the other memory plane. The end of a program or an erase cycle is detected by the Ready/Busy pin, Data Polling or by the toggle bit. The VPP pin provides faster program/erase times. With VPP at 5.0V or 12.0V, the program and erase operations are accelerated. A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Byte/Word Program) is exited by powering down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back to VCC. Erase and Erase Suspend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. When using the AT49BV1604A(T) pinout configuration, the device always operates in the word mode. In the AT49BV/LV1614A(T) configuration, the BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at logic "1", the device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic "0", the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tristated, and the I/O15 pin is used as an input for the LSB (A-1) address function.
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Block Diagram
I/O0 - I/O15/A-1
OUTPUT BUFFER
INPUT BUFFER
OUTPUT MULTIPLEXER
A0 - A19
INPUT BUFFER
DATA REGISTER
IDENTIFIER REGISTER
STATUS REGISTER
COMMAND REGISTER
ADDRESS LATCH DATA COMPARATOR
CE WE OE RESET BYTE
RDY/BUSY WRITE STATE MACHINE
Y-DECODER
Y-GATING
PROGRAM/ERASE VOLTAGE SWITCH
VPP
VCC GND X-DECODER
PLANE B SECTORS
PLANE A SECTORS
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AT49BV1604A(T)/1614A(T)
Device Operation
READ: The AT49BV/LV16X4A(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table (I/O8 - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of memory bits is a logical "1". The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command. CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is tEC. If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sectors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched on the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a section is tSEC. When the sector programming lockdown feature is not enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a sector that has been protected will result in the operation terminating in 2 s. BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical "0") on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is completed after the specified tBP cycle time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a program cycle. VPP PIN: The circuitry of the AT49BV/LV16X4A(T) is designed so that the device can be programmed or erased from the VCC power supply or from the VPP input pin. When VPP is less than or equal to the VCC pin, the device selects the V CC supply for programming and erase
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operations. When the VPP pin is greater than the V CC supply, the device will select the V PP input as the power supply for programming and erase operations. The device will allow for some variations between the VPP input and the VCC power supply in its selection of VCC or VPP for program or erase operations. If the VPP pin is within 0.3V of VCC for 2.65V < VCC < 3.3V, then the program or erase operations will use VCC and disregard the VPP input signal. When the VPP signal is used to accelerate program and erase operations, the VPP must be in the 5V 0.5V or 12V 0.5V range to ensure proper operation. The Vpp pin can be left unconnected. SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; any sector's usage as a write protected region is optional to the user. At power-up or reset all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed. SECTOR LOCKDOWN DETECTION: A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation. SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to interrupt a sector erase operation and then program or read data from a different sector within the same plane. Since this device has a dual-plane architecture, there is no need to use the Erase Suspend feature while erasing a sector when you want to read data from a sector in the other plane. After the Erase Suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. After the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. The system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command, which does require the plane address (determined by A18 and A19). The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see "Operating Modes" on page 12 (for hardware operation) or "Software Product Identification Entry/Exit" on page 20. The manufacturer and device codes are the same for both modes.
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AT49BV1604A(T)/1614A(T)
128-BIT PROTECTION REGISTER: The AT49BV/LV16X4A(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the Command Definition table on page 8. To lock out block B, the four-bus cycle Lock Protection Register command must be used as shown in the Command Definition table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don't cares. Please see the "Protection Register Addressing Table" on page 9 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After reading the protection register, the Product ID Exit command must be given prior to performing any other operation. DATA POLLING: The AT49BV/LV16X4A(T) features Data Polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte/word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a "0" on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. Please see "Status Bit Table" on page 21 for more details. TOGGLE BIT: In addition to Data Polling, the AT49BV/LV16X4A(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the same memory plane will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. An additional toggle bit is available on I/O2, which can be used in conjunction with the toggle bit that is available on I/O6. While a sector is erase suspended, a read or a program operation from the suspended sector will result in the I/O2 bit toggling. Please see "Status Bit Table" on page 21 for more details. RDY/BUSY: For the AT49BV/LV1614A(T), an open-drain Ready/Busy output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open-drain connection allows for OR-tying of several devices to the same RDY/BUSY line. HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against inadvertent programs to the AT49BV/LV16X4A(T) in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) V CC power-on delay: once V CC has reached the VCC sense level, the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. INPUT LEVELS: While operating with a 2.65V to 3.3V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V. OUTPUT LEVELS: For the AT49BV1604A(T), output high levels (VOH) are equal to VCCQ 0.2V (not VCC). For 2.65V - 3.3V output levels, VCCQ must be tied to VCC. For 1.8V - 2.2V output levels, VCCQ must be regulated to 2.0V 10%, while VCC must be regulated to 2.65V - 3.0V (for minimum power).
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Command Definition in Hex(1)
Command Sequence Read Chip Erase Sector Erase Byte/Word Program Enter Single Pulse Program Mode Single Pulse Byte/Word Program Sector Lockdown Erase Suspend Erase Resume Product ID Entry Product ID Exit(6) Product ID Exit(6) Program Protection Register Lock Protection Register - Block B Status of Block B Protection Bus Cycles 1 6 6 4 6 1 6 1 1 3 3 1 4 4 4 1st Bus Cycle Addr Addr 555 555 555 555 Addr 555 XXX PA(5) 555 555 XXX 555 555 555 Data DOUT AA AA AA AA DIN AA B0 30 AA AA F0 AA AA AA AAA AAA AAA 55 55 55 555 555 555 C0 C0 90 Addr 080 80 DIN X0 DOUT(7) AAA AAA 55 55 555 555 90 F0 AAA 55 555 80 555 AA AAA 55 SA(3)(4) 60 AAA (2) AAA AAA AAA 55 55 55 55 555 555 555 555 80 80 A0 80 555 555 Addr 555 AA AA DIN AA AAA 55 555 A0 AAA AAA 55 55 555 SA(3)(4) 10 30 2nd Bus Cycle Addr Data 3rd Bus Cycle Addr Data 4th Bus Cycle Addr Data 5th Bus Cycle Addr Data 6th Bus Cycle Addr Data
Notes:
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are Don't Care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are Don't Care in the word mode. Address A19 through A11 and A-1 are Don't Care in the byte mode. 2. Since A11 is a Don't Care, AAA can be replaced with 2AA. 3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see pages 10 and 11 for details). 4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled. 5. PA is the plane address (A19-A18). 6. Either one of the Product ID Exit commands can be used. 7. If data bit D1 is "0", block B is locked. If data bit D1 is "1", block B can be reprogrammed.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE and VPP with Respect to Ground ...................................-0.6V to +13.0V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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AT49BV1604A(T)/1614A(T)
Protection Register Addressing Table
Word 0 1 2 3 4 5 6 7 Note: Use Factory Factory Factory Factory User User User User Block A A A A B B B B A7 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 1 A2 0 0 0 1 1 1 1 0 A1 0 1 1 0 0 1 1 0 A0 1 0 1 0 1 0 1 0
1. All address lines not specified in the above table must be 0 when accessing the protection register, i.e., A19 - A8 = 0.
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AT49BV/LV1604A/1614A - Sector Address Table
x8 Plane A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B B B B B B B B B Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Size (Bytes/Words) 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K Address Range (A19 - A-1) 000000 - 001FFF 002000 - 003FFF 004000 - 005FFF 006000 - 007FFF 008000 - 009FFF 00A000 - 00BFFF 00C000 - 00DFFF 00E000 - 00FFFF 010000 - 01FFFF 020000 - 02FFFF 030000 - 03FFFF 040000 - 04FFFF 050000 - 05FFFF 060000 - 06FFFF 070000 - 07FFFF 080000 - 08FFFF 090000 - 09FFFF 0A0000 - 0AFFFF 0B0000 - 0BFFFF 0C0000 - 0CFFFF 0D0000 - 0DFFFF 0E0000 - 0EFFFF 0F0000 - 0FFFFF 100000 - 10FFFF 110000 - 11FFFF 120000 - 12FFFF 130000 - 13FFFF 140000 - 14FFFF 150000 - 15FFFF 160000 - 16FFFF 170000 - 1EFFFF 180000 - 18FFFF 190000 - 19FFFF 1A0000 - 1AFFFF 1B0000 - 1BFFFF 1C0000 - 1CFFFF 1D0000 - 1DFFFF 1E0000 - 1EFFFF 1F0000 - 1FFFFF x16 Address Range (A19 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - F7FFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF
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AT49BV/LV1604AT/1614AT - Sector Address Table
x8 Plane B B B B B B B B B B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Size (Bytes/Words) 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 64K/32K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K 8K/4K Address Range (A19 - A-1) 000000 - 00FFFF 010000 - 01FFFF 020000 - 02FFFF 030000 - 03FFFF 040000 - 04FFFF 050000 - 05FFFF 060000 - 06FFFF 070000 - 07FFFF 080000 - 08FFFF 090000 - 09FFFF 0A0000 - 0AFFFF 0B0000 - 0BFFFF 0C0000 - 0CFFFF 0D0000 - 0DFFFF 0E0000 - 0EFFFF 0F0000 - 0FFFFF 100000 - 10FFFF 110000 - 11FFFF 120000 - 12FFFF 130000 - 13FFFF 140000 - 14FFFF 150000 - 15FFFF 160000 - 16FFFF 170000 - 17FFFF 180000 - 18FFFF 190000 - 19FFFF 1A0000 - 1AFFFF 1B0000 - 1BFFFF 1C0000 - 1CFFFF 1D0000 - 1DFFFF 1E0000 - 1EFFFF 1F0000 - 1F1FFF 1F2000 - 1F3FFF 1F4000 - 1F5FFF 1F6000 - 1F7FFF 1F8000 - 1F9FFF 1FA000 - 1FBFFF 1FC000 - 1FDFFF 1FE000 - 1FFFFF x16 Address Range (A19 - A0) 00000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - F8FFF F9000 - F9FFF FA000 - FAFFF FB000 - FBFFF FC000 - FCFFF FD000 - FDFFF FE000 - FEFFF FF000 - FFFFF
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DC and AC Operating Range
AT49BV/LV16X4A(T)-70 Operating Temperature (Case) VCC Power Supply Ind. -40C - 85C 2.65V to 3.3V/3.0V to 3.6V AT49BV/LV16X4A(T)-90 -40C - 85C 2.65V to 3.3V/3.0V to 3.6V
Operating Modes
Mode Read Program/Erase
(2)
CE VIL VIL VIH X
OE VIL VIH X
(1)
WE VIH VIL X VIH X X X
RESET VIH VIH VIH VIH VIH VIH VIL
VPP X VPP(6) X X X X X
Ai Ai Ai X
I/O DOUT DIN High-Z
Standby/Program Inhibit Program Inhibit
X VIL VIH X
X Output Disable Reset Product Identification Hardware VIL X X
High-Z X High-Z
VIL
VIH
VIH
A1 - A19 = V IL, A9 = V H(3), A0 = V IL A1 - A19 = VIL, A9 = V H(3), A0 = V IH A0 = VIL, A1 - A19 = VIL A0 = VIH, A1 - A19 = VIL
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4)
Software(5)
VIH
Notes:
X can be VIL or VIH. Refer to AC programming waveforms on page 19. VH = 12.0V 0.5V. Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: C0H (x8)-AT49BV/LV16X4A; 00C0H (x16)-AT49BV/LV16X4A; C2H (x8)-AT49BV/LV16X4AT; 00C2H (x16)-AT49BV/LV16X4T. 5. See details under "Software Product Identification Entry/Exit" on page 20. 6. VPP can be left unconnected or 0V VPP 3.3V. For faster erase/program operations, VPP can be set to 5.0V 0.5V or 12V 0.5V.
1. 2. 3. 4.
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AT49BV1604A(T)/1614A(T)
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AT49BV1604A(T)/1614A(T)
DC Characteristics
Symbol ILI ILO ISB1 ISB2 ISB3 ICC
(1)(2)
Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Standby Current TTL VCC Active Read Current VCC Programming Current (VPP = VCC ) VPP Input Load Current VCC Programming Current (VPP = 5.0V 0.5V) VPP Programming Current (VPP = 5.0V 0.5V) VCC Programming Current (VPP = 12.0V 0.5V) VPP Programming Current (VPP = 12.0V 0.5V) Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage
Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to V CC CE = 2.0V to VCC CE = 2.0V to VCC, VCC = 2.85V f = 5 MHz; IOUT = 0 mA, 3.3V V CC
Min
Max 10 10 10 1 10 30 45
Units A A A mA A mA mA A A mA mA mA mA V V
ICC1 IPP1 ICC2 IPP2 ICC3 IPP3 VIL VIH VOL1 VOL2 VOH1
VPP = 0V, VCC = 3.0V VPP = VCC = 3.0V
10 10 40 5 40 6 0.6 2.0
IOL = 2.1 mA IOL = 1.0 mA IOH = -400 A VCCQ < 2.6V VCCQ 2.6V VCCQ < 2.6V VCCQ 2.6V VCCQ - 0.2 [AT49BV1604A(T)] 2.4 [AT49BV1604A(T)] 2.4 [AT49BV/LV1614A(T)] VCCQ - 0.1 [AT49BV1604A(T)] 2.5 [AT49BV1604A(T)] 2.5 [AT49BV/LV1614A(T)] IOH = -400 A IOH = -400 A IOH = -100 A
0.45 0.20
V V V V V V V V
Output High Voltage
VOH2
Output High Voltage
IOH = -100 A IOH = -100 A
Note:
1. In the erase mode, ICC is 50 mA. 2. For 3.3V < VCC < 3.6V, ICC (max) = 35 mA.
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AC Read Characteristics
AT49BV/LV16X4A(T)-70 Symbol tACC tCE
(1) (2)
AT49BV/LV16X4A(T)-90 Min Max 90 90 0 0 0 40 25 Units ns ns ns ns ns 100 ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first RESET to Output Delay
Min
Max 70 70
tOE
0 0 0
35 25
tDF(3)(4) tOH tRO
100
AC Read Waveforms(1)(2)(3)(4)
ADDRESS ADDRESS VALID
CE
tCE OE tOE tDF tACC tOH
RESET HIGH Z
tRO OUTPUT VALID
OUTPUT
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.
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AT49BV1604A(T)/1614A(T)
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AT49BV1604A(T)/1614A(T)
Input Test Waveforms and Measurement Level
tR, tF < 5 ns
Output Test Load
Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
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AC Byte/Word Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Setup Time Data, OE Hold Time Write Pulse Width High Min 0 40 0 0 40 30 0 30 Max Units ns ns ns ns ns ns ns ns
AC Byte/Word Load Waveforms
WE Controlled
CE Controlled
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AT49BV1604A(T)/1614A(T)
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AT49BV1604A(T)/1614A(T)
Program Cycle Characteristics
Symbol tBP tBPVPP tAS tAH tDS tDH tWP tWPH tWC tSR/W tRP tRH tEC tECVPP tSEC tEPS Parameter Byte/Word Programming Time (0V < VPP < 4.5V) Byte/Word Programming Time (VPP > 4.5V) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Write Pulse Width High Write Cycle Time Latency between Read and Write Operations Reset Pulse Width Reset High Time before Read Chip Erase Cycle Time (VPP < 4.5V) Chip Erase Cycle Time (VPP > 4.5V) Sector Erase Cycle Time (VPP < 4.5V) Erase or Program Suspend Time 300 0 40 30 0 40 30 70 50 500 50 12 6 400 15 Min Typ 20 10 Max 50 25 Units s s ns ns ns ns ns ns ns ns ns ns seconds seconds ms s
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP tWPH tBP
WE
t
tAS
tAH
555 AAA
tDH
555 ADDRESS
SR/W
A0 - A20
VALID READ ADDRESS
tWC
tDS
tACC AA 55 A0 INPUT DATA OUTPUT DATA
DATA
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1411F-FLASH-03/02
Sector or Chip Erase Cycle Waveforms
OE (1) CE
tWP tWPH t EC
WE
tSR/W tAS tAH
555 AAA
tDH
555 555 AAA Note 2 ADDRESS VALID
A0 - A20
tWC
tDS
AA 55 80 AA 55 Note 3 OUTPUT VALID
DATA
Notes:
WORD 0
WORD 1
WORD 2
WORD 3
WORD 4
WORD 5
t ACC
1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased. (See note 3 under Command Definitions.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
18
AT49BV1604A(T)/1614A(T)
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AT49BV1604A(T)/1614A(T)
Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in "AC Read Characteristics" on page 14.
0
ns
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in "AC Read Characteristics" on page 14. 50 0 Min 10 10 Typ Max Units ns ns ns ns ns
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
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1411F-FLASH-03/02
Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 555
Sector Lockdown Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 555
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 90 TO ADDRESS 555
LOAD DATA 80 TO ADDRESS 555
ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
LOAD DATA AA TO ADDRESS 555
Software Product Identification Exit(1)(6)
LOAD DATA AA TO ADDRESS 555 OR LOAD DATA F0 TO ANY ADDRESS
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 55 TO ADDRESS AAA
EXIT PRODUCT IDENTIFICATION MODE(4)
LOAD DATA 60 TO SECTOR ADDRESS
PAUSE 200 s(2)
LOAD DATA F0 TO ADDRESS 555
Notes:
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex), A-1, and A11 - A19 (Don't Care). 2. Sector Lockdown feature enabled.
EXIT PRODUCT IDENTIFICATION MODE(4)
Notes:
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex), A-1, and A11 - A19 (Don't Care). A1 - A19 = VIL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. Additional Device Code is read for address 0003H The device does not remain in identification mode if powered down. The device returns to standard operation mode. Manufacturer Code: 1FH(x8); 001FH(x16) Device Code: C0H (x8) - AT49BV/LV16X4A; 00C0H (x16) - AT49BV/LV16X4A; C2H (x8) - AT49BV/LV16X4AT; 00C2H (x16) - AT49BV/LV16X4AT. Additional Device Code: C8H (x8) - AT49BV/LV16X4A(T) 00C8H (x16) - AT49BV/LV16X4A(T) Either one of the Product ID Exit commands can be used.
2.
3. 4. 5.
6.
20
AT49BV1604A(T)/1614A(T)
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AT49BV1604A(T)/1614A(T)
Status Bit Table
Status Bit I/O7 Read Address In While Plane A Plane B Plane A I/O6 Plane B Plane A I/O2 Plane B
Programming in Plane A Programming in Plane B
I/O7 DATA
DATA I/O7
TOGGLE DATA
DATA TOGGLE
1 DATA
DATA 1
Erasing in Plane A Erasing in Plane B
0 DATA
DATA 0
TOGGLE DATA
DATA TOGGLE
TOGGLE DATA
DATA TOGGLE
Erase Suspended & Read Erasing Sector Erase Suspended & Read Non-erasing Sector
1 DATA
1 DATA
1 DATA
1 DATA
TOGGLE DATA
TOGGLE DATA
Erase Suspended & Program Non-erasing Sector in Plane A Erase Suspended & Program Non-erasing Sector in Plane B
I/O7
DATA
TOGGLE
DATA
TOGGLE
DATA
DATA
I/O7
DATA
TOGGLE
DATA
TOGGLE
21
1411F-FLASH-03/02
AT49BV1604A(T)/1614A(T) Ordering Information
tACC (ns) 70 90 70 90 70 90 70 90 ICC (mA) Active 25 25 25 25 25 25 25 25 Standby 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 Ordering Code AT49BV1604A-70CI AT49BV1604A-70TI AT49BV1604A-90CI AT49BV1604A-90TI AT49BV1604AT-70CI AT49BV1604AT-70TI AT49BV1604AT-90CI AT49BV1604AT-90TI AT49BV1614A-70CI AT49BV1614A-70TI AT49BV1614A-90CI AT49BV1614A-90TI AT49BV1614AT-70CI AT49BV1614AT-70TI AT49BV1614AT-90CI AT49BV1614AT-90TI Package 45C1 48T 45C1 48T 45C1 48T 45C1 48T 48C5 48T 48C5 48T 48C5 48T 48C5 48T Operation Range Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C)
AT49LV1614A(T) Ordering Information
tACC (ns) 70 70 ICC (mA) Active 25 25 Standby 0.01 0.01 Ordering Code AT49LV1614A-70CI AT49LV1614A-70TI AT49LV1614AT-70CI AT49LV1614AT-70TI Package 48C5 48T 48C5 48T Operation Range Industrial (-40 to 85C) Industrial (-40 to 85C)
Package Type 45C1 48C5 48T 45-ball, Plastic Chip-size Ball Grid Array Package (CBGA) 48-ball, Plastic Chip-size Ball Grid Array Package (CBGA) 48-lead, Plastic Thin Small Outline Package (TSOP)
22
AT49BV1604A(T)/1614A(T)
1411F-FLASH-03/02
AT49BV1604A(T)/1614A(T)
Packaging Information
45C1 - CBGA
Dimensions in Millimeters and (Inches). Controlling dimension: millimeters.
6.60 (0.260) 6.40 (0.252)
A1 ID
7.60 (0.299) 7.40 (0.291)
0.15 (0.006)MIN 1.20 (0.047) MAX 0.625 (0.025) REF
8 7 6
5.25 (0.207)
5 4 3 2 1
1.875(0.074) REF
A B C
3.75 (0.148)
D
0.75 (0.0295) BSC NON-ACCUMULATIVE
E F
0.30 (0.014) DIA BALL TYP 0.75 (0.0295) BSC NON-ACCUMULATIVE
4/11/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 45C1, 45-ball (8 x 6 Array), 0.75 mm Pitch, 6.5 x 7.5 x 1.2 mm Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 45C1 REV. A
R
23
1411F-FLASH-03/02
48C5 - CBGA
Dimensions in Millimeters and (Inches). Controlling dimension: millimeters.
6.10 (0.240) 5.90 (0.232)
A1 ID
8.10 (0.319) 7.90 (0.311)
0.25 (0.010)MIN
TOP VIEW
1.20 (0.047) MAX
SIDE VIEW
1.00(0.039) REF
6
4.00(0.157)
5 4 3 2 1
1.20 (0.047) REF
A B C
0.80 (0.0315) BSC NON-ACCUMULATIVE
D E F G H
5.60 (0.220)
0.80 (0.0315) BSC NON-ACCUMULATIVE
0.40 (0.016) DIA BALL TYP
BOTTOM VIEW
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 48C5, 48-ball (6 x 8 Array), 0.80 mm Pitch, 6 x 8 x 1.2 mm Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 48C5 REV. A
R
24
AT49BV1604A(T)/1614A(T)
1411F-FLASH-03/02
AT49BV1604A(T)/1614A(T)
48T - TSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation DD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 19.80 18.30 11.90 0.50 NOM - - 1.00 20.00 18.40 12.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 12.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 48T REV. B
R
25
1411F-FLASH-03/02
Atmel Headquarters
Corporate Headquarters
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600
Atmel Operations
Memory
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Microcontrollers
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e-mail
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Web Site
http://www.atmel.com
(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
1411F-FLASH-03/02 /xM

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